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General Description

The EM78P372N is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. The device has an on-chip 2K13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory code. Three Code option bits are also available to meet user s requirements.

With enhanced OTP-ROM features, the EM78P372N provides a convenient way of developing and verifying user s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code.

Features

CPU Configuration

2Kx13 bits on-chip ROM

80x8 bits on-chip registers (SRAM)

8-level stacks for subroutine nesting

4 programmable Level Voltage Detector (LVD): 4.5V, 4.0V, 3.3V, 2.2V

3 programmable Level Voltage Reset (LVR): 4.0V, 3.5V, 2.7V

Less than 1.5 mA at 5V / 4 MHz

Typically 15 μA, at 3V / 32kHz

Typically 2 μA, during Sleep mode

4 programmable Level Voltage Detector (LVD): 4.5V, 4.0V, 3.3V, 2.2V

3 programmable Level Voltage Reset (LVR): 4.0V, 3.5V, 2.4V

Less than 1.5 mA at 5V / 4 MHz

Typically 15 μA, at 3V / 32kHz

Typically 2 μA, during Sleep mode

4 programmable Level Voltage Detector (LVD): 4.5V, 4.0V, 3.3V, 2.2V

3 programmable Level Voltage Reset (LVR): 4.0V, 3.5V, 2.4V

Less than 1.5 mA at 5V / 4 MHz

Typically 15 μA, at 3V / 32kHz

Typically 2 μA, during Sleep mode

3 programmable Level Voltage Reset (LVR): 4.0V, 3.5V, 2.4V

Less than 1.5 mA at 5V / 4 MHz

Typically 15 μA, at 3V / 32kHz

Typically 2 μA, during Sleep mode

I/O port configuration

3 bidirectional I/O ports: P5, P6, P7

18 I/O pins & 1I pin

Wake-up port: P5

8 programmable pull-down I/O pins

16 programmable pull-high I/O pins

8 programmable open-drain I/O pins

14 programmable high-sink current I/O pins

External interrupt：P60

Operating Voltage and T